Chip Architecture for Data Sorting Using Recursive Algorithm
| dc.contributor.author | Megha Agarwal | |
| dc.contributor.author | Indra Gupta | |
| dc.date.accessioned | 2026-01-08T07:53:15Z | |
| dc.date.available | 2026-01-08T07:53:15Z | |
| dc.date.issued | 2010-04 | |
| dc.description.abstract | “This paper suggests a way to implement recursive algorithm on hardware with an example of sorting of numeric data. Every recursive call/return needs a mechanism to store/restore parameters, local variables and return addresses respectively. Also a control sequence is needed to control the flow of execution as in case of recursive call and recursive return. The number of states required for the execution of a recursion in hardware can be reduced compared with software. This paper describes all the details that are required to implement recursive algorithm in hardware. For implementation, all the entities are designed using VHDL and are synthesized, configured on Spartan-2 XC2S200-5PQ208. “ | |
| dc.identifier.issn | 0976-545X | |
| dc.identifier.issn | 2456-3226 | |
| dc.identifier.other | https://doi.org/10.15415/jtmge.2010.11006 | |
| dc.identifier.uri | https://demodspace.chitkara.edu.in/handle/123456789/343 | |
| dc.language.iso | en | |
| dc.publisher | Chitkara University Publications | |
| dc.subject | Binary search tree | |
| dc.subject | Field programmable gate arrays (FPGA) | |
| dc.subject | Recurssive Algorythms | |
| dc.subject | very high speed integrated circuits hardware description language (VHDL) | |
| dc.title | Chip Architecture for Data Sorting Using Recursive Algorithm | |
| dc.type | Article |